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simplifying system integration tm 73s1210 f evaluation board lite user guide august 18 , 2009 rev. 1. 1 ug_12 10 f_ 0 44 downloaded from: http:///
73s1210f evaluation board lite user guide ug_1210f_044 2 rev. 1.1 ? 2009 teridian semiconductor corporation. all rights reserved. teridian semiconductor co rporation is a registered trademark of teridian semiconductor corporation. simplifying system integration is a trademark of teridian semiconductor corporation. microsoft, windows and vista are a registered trademark s of microsoft corporation. signum is a trademark of signum systems corporation. keil is a trademark of a rm ? ltd. all other trademarks are the property of their respective owners. teridian semiconductor corporation makes no warranty for the use of its products, ot her than expressly contained in the companys warranty detailed in the teridian semiconductor corporation standard terms and conditions. the company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any ti me without notice and does not make any commitment to update the information contained herein. accord ingly, the reader is cautioned to verify that this document is current by comparing it to th e latest version on http://www.teridian.com or by checking with your sales representative. teridian semiconductor corp., 6440 oak canyon, suite 100, irvine, ca 92618 tel (714) 508 - 8800, fax (714) 5 08 - 8877, http://www.teridian.com downloaded from: http:///
ug_1 210f_044 73s1210f evaluation board lite user guide rev. 1.1 3 table of contents 1 introduction ................................................................................................................................... 4 1.1 evaluation board lite package contents .............................................................................. 5 1.2 evaluation board lite features ............................................................................................. 5 1.3 recommended equipment and test tools ............................................................................ 5 2 evaluation board lite setup ......................................................................................................... 6 2.1 using the evaluation board lite with an emulation tool ........................................................ 7 2.2 loading user code into the evaluation board - lite ................................................................ 7 3 using the pccid appl ication ........................................................................................................ 9 3.1 host demonstration software installation .............................................................................. 9 4 evaluation board lite hardware description ............................................................................. 10 4.1 jumpers, switches and test points ..................................................................................... 10 4.2 sch ematic ........................................................................................................................... 13 4.3 pcb layouts ....................................................................................................................... 14 4.4 bill of materials ................................................................................................................... 20 4.5 schematic information ........................................................................................................ 22 4.5.1 reset circuit .............................................................................................................. 22 4.5.2 oscillator ................................................................................................................... 22 4.5.3 smart card interface ................................................................................................ . 23 5 ordering information ................................................................................................................... 24 6 related documentation ............................................................................................................... 24 7 contact information ..................................................................................................................... 24 revision history .................................................................................................................................. 25 figures figure 1: 73s1210f evaluation board lite ............................................................................................... 4 figure 2: 73s1210f evaluati on board lite basic connections ................................................................ . 6 figure 3: emulator window showing reset and erase buttons ........................................................... 8 figure 4: emulator window showing erased flash memory and file load menu ..................................... 8 figure 5: 73s1210f evaluation board lite jumper, switch and test point locations ............................. 12 fig ure 6: 73s1210f evaluation board lite electrical schematic ............................................................. 13 figure 7: 73s1210f evaluation board lite top view (silkscreen) .......................................................... 14 figure 8: 73s1210f evaluation board lite bottom view (silkscreen) ..................................................... 15 figure 9: 73s1210f evaluation board lite top signal layer .................................................................. 16 figure 10: 73s1210f evaluation board lite middle layer 1 C ground plane .......................................... 17 figure 11: 73s1210f evaluation board lite middle layer 2 C supply plane ........................................... 18 figure 12: 73s1210f evaluation board lite bottom signal layer ........................................................... 19 figure 13: external components for reset .......................................................................................... 22 figure 14: oscillator circuit .................................................................................................................... 22 figure 15: smart card connections ....................................................................................................... 23 tables table 1: flash programming interface signals ......................................................................................... 7 table 2: evaluation board lite jumper, switch and test point description ............................................. 10 table 3: 73s1210f evaluation board lite bill of materials ...................................................................... 20 downloaded from: http:///
73s1210f evaluation board lite user guide ug_1210f_044 4 rev. 1.1 1 introduction the t eridian semiconductor corporation (tsc) 73s1210f evaluation board - lite is used to demonstrate the capabilities of the 73s1210f smart card controller device . it has b een designed to operate either as a standalone or as a development platform. the 73s1210f evaluation board lite can be programmed to run any of the teridian turnkey appl ication s or a user - developed custom application. teridian provides its usb ccid appli cation preloaded o n the board and an emv testing application on the cd . a pplications can be downloaded through the in - circuit - emulator (ice) or through the tsc flash programmer model tfp2. as a development tool, t he evaluation b oard lite has been designe d to operate in conjunction with an ice to develop and debug 73s1210f based embedded applications. the 73s1210f evaluation board lite uses the same pwb as the 73s1217f. the 73s1217f has some features that the73s1210f does not contain. these include th e 32 khz oscillator and usb interface. these features are depopulated on the 73s1210f evaluation board - lite. figure 1 : 73s1210f evaluation board lite downloaded from: http:///
ug_1 210f_044 73s1210f evaluation board lite user guide rev. 1.1 5 1.1 evaluation board lite package contents the 73s1210f evaluation board lite package contains the following: ? 73s1210f evaluation b oard lite : 4 - layer, square pc b as shown i n figure 1 , containing the 73s1210f with the preloaded turnkey pseudo - ccid (pccid) program . ? 5 vdc/1,00 0 ma universal wall transformer. ? serial cable: db9, male/female, 2 meter length (digi - key ae1379 - nd). ? cd containing documentation (data sheet, board schematics, bom and layout), evaluation code, and utilities. ? the 73s1210f evaluation board lite quick start guide document . 1.2 evaluation board lite features the 73s1210f evaluation board lite (see figure 1) includes the following features : ? rs - 232 interface ? single smart card interface ? power interface ? ice/programmer interface ? on/off swi tch ? 1 led 1.3 recommended equipment and test tools the following equipment and tools (not provided) are recommended for use with the 73s1210f evaluation board lite package : ? for f unctional e valuation : pc with microsoft ? windows ? xp or vista ? equipped with an rs232 (com) port with db9 connector. ? for software development (mpu code) ? signum ? ice (in circuit emulator): adm - 51. refer to http://signum.temp.veriohosting.com/signum.htm . ? keil ? 8051 c compile r kit: ca51. refer to http://www.keil.com/c51/ca51kit.htm and http://www.keil.com/product/sales.htm . downloaded from: http:///
73s1210f evaluation board lite user guide ug_1210f_044 6 rev. 1.1 2 evaluation board lite setup figure 2 shows the basic connections of the evaluation b oard lite with the external equipment. the power supply input (vbat) provides back - up power for those applications capable of using it. when a power supply is connected to vbat, the on/off switch, s2, turns the power supply to the 73s1210f on or off. ? connect pj1 on the board to any ac - dc converter block able to generate a dc power supply of 4.0 v to 6.5 v and 400 ma the communication to an external host is accommodated via a standard rs - 232 serial interface (tx/rx only) . figure 2 : 73s1210f evaluation board lite basic connections downloaded from: http:///
ug_1 210f_044 73s1210f evaluation board lite user guide rev. 1.1 7 2.1 using the evaluation board lite with an emulation tool the 73s1210f evaluation board li te has been designed to operate with an in - circuit - emulator (ice) from signum systems (model adm - 51). the signum system pod has a ribbon cable that must be directly attached to connector j 2. signum systems offers different pod options depending on user needs. the standard pod al lows users to perform typical emulator functions such as symbolic debugging, in - line breakpoints, memory e xamination/modification, etc. other pod options enable code trace capability and/or complex breakpoints at an additional co st. when using an ice, the board must be externally powered (and turned on via the on/off switch. the power led d4 will indicate the power status. 2.2 loading u ser c ode into the evaluation board - lite hardware interface for programming the signals listed i n table 1 are necessary for communication between the tfp2 flash programmer or ice and the 73s1210f . table 1 : flash programming interface signals signal direction function e_tclk output fr om 73s1210f data clock e_rxtx bi - directional data input/output e_rst 1 bi - directional flash downloader reset (active low) 1 the e_rst signal should only be driven by the tfp2 when enabling these interface signals. the tfp2 must release e_rst at all other times. the signals in table 1 , along with 3.3 v and gnd, are available on the emulator header j2. production modules may be equipped with much simpler programming connectors, e.g. a 5x1 header . programming of the flash memory requires either the signum systems adm51 in - circuit emulator or the tsc flash programmer model tfp2 provided by teridian . loading code with the in - circuit emulator if firmware exists in the 73s1210f flash memory, the memory must be erased before loading a new file into memory. in order to erase the flash memory, the reset button in the emulator software must be clicked followed by the erase button ( see figure 3 ). once the flash memory is erased, the new file can be loaded using the load command in the file menu . the dialog box shown in figure 4 makes it possible to select the file to be loaded by clicking the browse button. once the file is selected, pressing the ok button loads the file into the flash memory of t he ic. at this point, the emulator probe (cable) can be removed. once the 73s1210f device is reset using the reset button on the evaluation board lite, the new code starts executing. loading code with the tsc flash programmer model tfp2 follow the instructions given in the tsc flash programmer model tfp2 user's manual . downloaded from: http:///
73s1210f evaluation board lite user guide ug_1210f_044 8 rev. 1.1 figure 3 : emulator window showing reset and erase buttons figure 4 : emulator window showing erased flash memory and file load menu reset button erase button downloaded from: http:///
ug_1 210f_044 73s1210f evaluation board lite user guide rev. 1.1 9 3 using the pccid application the p ccid firmware is pre - installed on the 73s1210f evaluation board. it requires a pc with the serial rs - 232 port. when powered - up, the board is able to run th e pccid demonstration host application which allows: ? smart card activation and deactivation, in iso or emv mode. ? smart card apdu commands to be exchanged with the smart card inserted in the board. ? starting a test sequence in order to test and evaluate the board performance against an emv test environment. 3.1 host demonstration software installation installation on windows xp follow these steps to install the software on a pc running windows xp: ? extract p ccid v z.zz release.zip (where z.zz is the latest version of the firmware release). o create an install directory. for example: c: \ tsc \ . o unzip pccid v z. zz release.zip to the just created folder. all applications and documentation needed to run the board with a windows pc will be loaded to this folder. ? plu g the supplied adapter into the 5v dc jack and a wall outlet. ? connect the serial cable between the host system and the 73s1210f evaluation board. ? press the on/off switch to turn the board on. ? run tscp - ccid.exe (located in the path - x :\ yyy \ pccid v z.zz release \ host applications \ w indows app \ app \ bin \ release ) on the host system to execute the host demonstration application (where x refers to the drive, yyy refers to the directory the installation .zip file was expanded to and z.zz is the latest version of the firmware release). at this point the application window should appear. for additional information reg arding the use of the teridian host application, refer to the pseudo - ccid host gui users guide (ug_12xxf_037). downloaded from: http:///
73s1210f evaluation board lite user guide ug_1210f_044 10 rev. 1.1 4 evaluation board lite hardware desc ription 4.1 jumpers, switches and test points table 2 describes the 73s1210f evaluation board lite jumpers, switches and test points . the item # in table 2 references figure 5 . the default setting column refers to setup for running pccid application. table 2 : evaluation board lite jumper, switch and test point description item # schematic and silkscreen referen ce default s etting name use 1 s1 reset button evaluation board main reset: asserts a hardware reset to the on - board 73s1210f. 2 s2 on / off button when using battery power (on pj1), turns on or off (toggles) power to the 73s1210f device. 3 tp8 vp t est point test point used for monitoring vp voltage. vp is 5.5 v when the 72s1210f is on. 4 tp2 icc test point smart card interface test points with ground pins. 5 tp1 vbat test point vbat input test point. 6 tp3 usr pin test points usr pin test poi nts. 7 pj1 connect dc jack vbat input power jack. vbat used as the primary power input must be between 4.0 v and 6. 5 v. vbat requires the use of the on/off switch to turn on the 72s1210f. 8 tp6 vdd test point vdd test point with ground. 9 j2 no conne ct in - circuit emulator connector this connector must be used when using an external in - circuit emulator (signum adm51). refer to the electrical schematic for pin assignments. 10 d5 rxd led reflects the activity on the serial rx: data going to the 73s121 0f. 11 tp4 insert rxd led jumper jumper inserted enables the rx led. jumper removed disables the rx led. 12 d6 txd led reflects the activity on the serial tx: data going from the 73s1210f. 13 jp2 vdd serial transceiver enable jumper jumper controls the rs - 232 transceiver shutdown function. there are three possible configurations: ? removed; places the rs - 232 transceiver chip in shutdown. ? inserted vdd; enables the rs - 232 transceiver. ? inserted usr6; allows the usr6 pin to control the rs - 232 transceiver sh utdown . 14 tp5 insert txd led jumper jumper inserted enables the tx led. jumper removed disables the tx led. downloaded from: http:///
ug_1 210f_044 73s1210f evaluation board lite user guide rev. 1.1 11 item # schematic and silkscreen referen ce default s etting name use 15 p1 connect db9 rs232 female socket this socket allows for connection of an rs232 cable to a computer. use crossed wires (rx/tx) cable. the evaluation board has an on - board level shifter (u7) to allow direct connection to a computer. 16 - board reference and serial number should be mentioned in any communication with teridian when requesting support. 17 d4 power led power led comes on wit h vdd. can be disabled by removing jp4. 18 jp4 insert power led disable inserting the jumper enables the power led with vdd. removing the jumper disables the power led. 19 d1 led0 73s1210f led0 output led. 20 tp7 vpc test point test point to monito r vpc. vpc is the input power source to the internal voltage converter. this voltage is derived from either vbus or vbat. see the 73s1210f datasheet for further information. 21 j1 smart card connector allows the evaluation board to communicate with a smart card using a standard (credit card size) format. this slot is connected to the 73s1210f external card interface. downloaded from: http:///
73s1210f development board users guide ug_1210f_044 12 rev. 1.1 figure 5 : 73s1210f evaluation board lite jumper, switch and test point locations downloaded from: http:///
ug_1210f_044 73s1210f evaluation board lite user guide rev. 1.1 13 4.2 schematic vdd c29 0.1uf r23 200k osc_out_32 osc_out_32 osc_out_32 osc_out_32 usr0 usr2 place r's close to u4 length and width of usb d+ and d- tracks should be matched and routed away from smart card clk and vccs usr4 serialport c4 osc_in_32 osc_in_32 osc_in_32 osc_in_32 gnd r21 24 c5 27p d+ tbus[3]tbus[3] isync/brkrq 1 2 jp4 d1 led c25 22pf vdd led0 vdd c24 22pf tbus[0] r5 10k vdd usr6 1 2 3 jp2 header 3_0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 j2 emulator if 232 shdnsel vdd r7 62 r9 62 r10 62 r13 62 r17 62 r15 62 r14 62 r16 62 c27 22pf c26 22pf tbus[1] c28 22pf r xtx tc lk tbus[2] r st_emu l 1 sy m1 logo vbus_monenable vbat vcc 1 rst 2 clk 3 c4 4 gnd 5 vpp 6 i/o 7 c8 8 sw-1 9 sw-2 10 j1 smart card connector c16 27pf c11 22pf c10 22pf smartcardslot #1 usr1 usr2 usr7 r3 100k usr5 usr6 usr4 usr3 1 2 3 4 5 6 7 8 tp3 header 8 1 tp8 vp r25 200k r1 0 r18 680 r19 680 dplus dminus vdd d5 led d6 led power leddisable rst d- gnd c9 should be as close as possible to pin 54 vcc tracks should be wider than 0.5mm. dminus usr6 usr0 +5vdc vbat dni dnidni dni dni dni dni dni mount holes for stand offs dni 1 g1 1 g2 1 g3 1 g4 c9 4.7uf 1 tp7 dni 1 2 tp4 rxd leddisable 1 2 s2 sw vpc txdtxdtxdtxdtxdtxdtxdtxd y2 12.000mhz r4 10 1 2 s1 sw txd leddisable 1 2 tp5 vdd osc_in_12 osc_in_12 osc_out_12 osc_out_12 osc_out_12 osc_in_12 osc_out_32 osc_in_32 r2 1m power io usr7 l1 10uh 1 2 jp1 reset status indicator + c13 10uf rxd c5 c6 and c7 should be located close to the smart card connector 1 1 2 2 3 3 pj1 +5vdc vdd 68 reset 1 sec 2 isbr 3 scl 5 sda 6 nc 7 nc 8 gnd 9 x12in 10 x12out 11 col0 12 col1 13 col2 14 anain 15 col3 16 r xd 17 txd 18 col4 19 usr7 20 row0 21 row1 22 usr6 23 row2 24 gnd 25 nc 26 nc 27 vdd 28 usr5 29 usr4 30 usr3 31 usr2 32 row3 33 usr1 34 usr0 35 row4 36 row5 37 erst 38 tc lk 39 vdd 40 tbus3 41 gnd 42 r xtx 43 tbus2 44 sclk 45 tbus1 46 sio 47 int3 48 int2 49 tbus0 50 test 51 off_req 52 pres 53 vp 54 clk 55 gnd 56 rst 57 vcc 58 aux2 59 aux1 60 i/o 61 vbus 62 on_off 63 vbat 64 vpc 65 lin 66 gnd 67 slug 69 led0 4 u4 73s1210f 1 tp1 vdd d4 led r24 680 clk and vcc tracks should be routed away from other smart card signals and should be surrounded by gnd. c17 1000pf 1 6 2 7 3 8 4 9 5 p1 db9_rs232 int2 c22 0.1uf clk y1 32.768khz c23 0.1uf c20 0.1uf c33 should be as close as possible to pin 65 c21 0.1uf on_off vdd c8 usr3 usr5 c30, c31 and c32 should be as close as possible to vdd pins on u4 c19 0.1uf vcc c7 0.47uf txd usr1 +5vdcunreg 1 2 tp6 d- 2 d+ 3 gnd 4 vcc 1 gnd 5 gnd 6 j3 usb_conn_4 c12 27pf c30 0.1uf c31 0.1uf vdd c32 0.1uf 1 2 3 4 5 6 7 8 9 10 11 12 tp2 header 2 x 4 r xd vbus r20 24 vdd usr2 usr7 usr3 usr1 usr0 usr6 usr4 usr5 usr2 usr0 usr3 usr1 install r6, r8, r11 and r12 for plug and play operation, do not install otherwise r11 0 vdd r6 0 r8 0 r12 0 c14 .1uf c1+ 28 c1- 25 c2+ 1 c2- 3 t1i n 24 t2i n 23 t3i n 22 t4i n 19 t5i n 17 r1outbf 16 r1out 21 r2out 20 r3out 18 gnd 2 mbaud 15 shdnb 14 enb 13 r3in 11 r2in 9 r1in 8 t1ou t 5 t2ou t 6 t3ou t 7 t4ou t 10 t5ou t 12 v- 4 v+ 27 vcc 26 u3 max3237cai r22 100k vdd dplusdplusdplusdplusdplusdplusdplusdplusdplusdplusdplusdplusdplusdplusdplusdplusdplus dplusdplusdplusdplusdplusdplusdplusdplusdplusdplusdplusdplusdplusdplusdplusdplusdplus dplusdplus vbusvbusvbusvbusvbusvbusvbusvbusvbusvbusvbusvbus c33 10uf c6 27p figure 6 : 73s1210f evaluation board lite electrical schematic downloaded from: http:///
73s1210f evaluation board lite user guide ug_1210f_044 14 rev. 1.1 4.3 pcb layouts figure 7 : 73s1210f evaluation board lite top view ( silkscreen ) downloaded from: http:///
ug_1210f_044 73s1210f evaluation board lite user guide rev. 1.1 15 figure 8 : 73s1210f ev aluation board lite bottom view ( silkscreen ) downloaded from: http:///
73s1210f evaluation board lite user guide ug_1210f_044 16 rev. 1.1 figure 9 : 73s1210f evaluation board lite top signal layer downloaded from: http:///
ug_1210f_044 73s1210f evaluation board lite user guide rev. 1.1 17 figure 10 : 73s12 10 f evaluation board lite middle layer 1 C ground plane downloaded from: http:///
73s1210f evaluation board lite user guide ug_1210f_044 18 rev. 1.1 figure 11 : 73s1210f evaluation board lite middle layer 2 C supply plane downloaded from: http:///
ug_1210f_044 73s1210f evaluation board lite user guide rev. 1.1 19 figure 12 : 73s1210f evaluation board lite bottom signal layer downloaded from: http:///
73s1210f evaluation board lite user guide ug_121 0f_044 20 rev. 1.1 4.4 bill of materials table 3 provides the bill of materials for the 73s12 10 f evaluation board lite schematic provided in figure 6 . table 3 : 73s1210f evaluation board lite bill of materials item q ty. reference part pcb f ootprint digi - key pa rt n umber part n umber manufacturer 1 3 c5,c6,c12,c16 27 pf 603 pcc270acvct - nd ecj - 1vc1h270j panasonic 2 1 c7 0.47 f 603 pcc2275ct - nd ecj - 1vb1a474k panasonic 3 1 c9 4.7 f 603 pcc2396ct - nd ecj - 1vb0j475k panasonic 4 5 c24,c25,c26,c27,c28 22 pf 603 pcc22 0acvct - nd ecj - 1vc1h220j panasonic 5 1 c13 10 f 3528 - 21 (eia) 478 - 1672 -1- nd tajb106k010r avx corporation 6 9 c14,c19,c20,c21,c22, c23,c30,c31,c32 0.1 f 603 445 - 1314 -1- nd c1608x7r1h104k tdk corporation 7 1 c17 1000 pf 603 pcc2151ct - nd ecj - 1vc1h102j panasonic 8 1 c33 10 f 805 pcc2225ct - nd ecj - 2fb0j106m panasonic 9 4 d1,d4,d5,d6 led 0805_diode 160 - 1414 -1- nd ltst - c170fkt lite - on inc 10 4 g1,g2,g3,g4 mthole mthole 11 5 jp1,tp4,jp4,tp5,tp6 header 5 x 1 pin s1011e - 36 - nd pbc36saan sullins 12 1 jp2 he ader 5 x 2 pin s2011e - 36 - nd pbc36daan sullins 13 1 j1 smart card connector itt/ccm02 - 2504 401 - 1715 - nd ccm02 - 2504lft itt industries 14 1 j2 emulator if ribbon6513 a3210 - nd 104068 -1 amp/tyco electronics 15 1 l1 10 h 1210 490 - 4059 -2- nd lqh32cn100k53 l mura ta electronics 16 1 pj1 +5vdc sc237 - nd rapc712x switchcraft 17 1 p1 db9_rs232 a32075 - nd 5745781 -4 amp/tyco electronics 18 5 r1,r6,r8,r11,r12 0 603 p0.0gct - nd erj - 3gey0r00v panasonic 19 1 r2 1 m 603 p1.0mgct - nd erj - 3geyj106v panasonic 20 1 r3 100 k 603 p100kgct - nd erj - 3geyj104v panasonic downloaded from: http:///
ug_1210f_044 73s1210f evaluation board lite user guide rev. 1.1 21 item q ty. reference part pcb f ootprint digi - key pa rt n umber part n umber manufacturer 21 1 r4 10 603 p10gct - nd erj - 3geyj100v panasonic 22 1 r5 10 k 603 p10kgct - nd erj - 3geyj103v panasonic 23 8 r7,r9,r10,r13,r14, r15,r16,r17 62 603 p62gct - nd erj - 3geyj620v panasonic 24 3 r18,r19,r24 680 603 p680gct - nd erj - 3geyj681v panasonic 25 1 r25 200 k 603 p200kgct - nd panasonic 26 2 s1,s2 sw pb p8051sct evq - pjx05m panasonic 27 3 tp1,tp7,tp8 header 2 x 4 s1011e - 36 - nd pbc36saan sullins 28 1 tp 2 header 2 x 4 s2011e - 36 - nd pbc36daan sullins 29 1 tp3 header 8 s1011e - 36 - nd pbc36saan sullins 30 1 u3 max3237cai sog.65m/28 max3237cai+ - nd max3237cai+ maxim 31 1 u4 73s1210f 68 qfn 73s1210f teridian 32 1 y2 12.000 mhz xtal/hc49us/.140h x1116 - nd ecs - 120 - 20 - 4xdn ecs downloaded from: http:///
73s1210f evaluation board lite user guide ug_1210f_044 22 rev. 1.1 4.5 schematic information this section provides recommendations on proper schematic design that will help in d esigning circuits that are functional and compatible with the pccid software library apis. 4.5.1 reset circuit the 73s1210f evaluati on board lite provides a reset pushbutton that can be used when prototyping and debugging software. the reset pin should be supported by the external compon ents shown in figure 13 . r8 should be around 10 . the capacitor c27 should be 10 f. r8 and c27 should be mounted as close as possible to the ic. c43 (1000 pf) is shown for eft protection and is optional. s27 sw 1 2 reset 3.3v reset + c27 10uf r10 10k r8 10 c43 1000pf figure 13 : external components for reset 4.5.2 oscillator the 73s1210f contain s a single oscillator for the primary system clock. the system clock should use a 12 mhz crystal to provide the proper system clock rates for the serial and smart card interfaces. th e system oscillator requires a 1 m parallel resistor to insure proper oscillator startup (see figure 14 ). figure 14 : oscillator circuit 73s1210f y3 12.000mhz r3 5 1m c36 22pf c44 22pf osc_out_12 osc_i n_12 downloaded from: http:///
ug_1210f_044 73s1210f evaluation board lite user gu ide rev. 1.1 23 4.5.3 smart card interface the smart card interface on the 73s1210f requires a few external components for proper operation. figure 15 shows the recommended smart card interface connections. the rst and clk signals should have 27 pf capacitors at the smart card connector . it is recommended that a 0 ? resistor be added in series with the clk signal. if necessary, in noisy environments, this resistor can be rep laced with a small resistor to create a rc filter on the clk signal to reduce clk noise. this filter can be used t o soften the cl ock edges and provide a cleaner clock for those environments where this could be problematic . the vcc output must have a 1.0 f capacitor at the smart card connector for proper operation. the vpc input is the power supp ly input for the smart card power. it is recom mended that both a 10 f and a 0.1 f capacitor are connected to provide proper decoupling for this input. lastly, the pres input on the 73s1210f contains a very weak pull down resistor. as a result, an additional external pull down resistor is recommended to prevent any system noise from triggering a false card event. the same holds true for the pres input, except a pull up resistor is utilized as the logic is inverted from the pres input. ? the smart card interface layout is important. the following gu idelines should be followed to provide the optimum smart card interface operation: ? route auxiliary signals away from card interface signals ? keep clk signal as short as possible and with few bends in the trace. keep route of the clk trace to one layer (avoid vias to other plane). keep clk trace away from other traces especially rs t and vcc. filtering of the clk trace is allowed for noise purpose. up to 30 pf to ground is allowed at the clk pin of the smart card connector. also, the zero series resisto r, r7, can be replaced for additional filtering (no more than 100 ). ? keep vcc trace as short as possible. make trace a minimum of 0.5 mm thick. also, keep vcc away from other traces especially rst and clk. ? keep clk trace away from vcc and rst traces. up to 30 pf to ground is allowed for filtering ? keep 0.1 f close to vdd pin of the device and directly take other end to ground ? keep 10 f and 0.1 f capacitors close to vpc pin of the device and directly take other end to ground ? keep 1.0 f close to vcc pin of the smart card connector and directly take other end to ground 1210 figure 15 : smart card connections downloaded from: http:///
73s1210f evaluation board lite user guide ug_1210f_044 24 rev. 1.1 5 ordering information part description order n umber 73s1210f 68 - pin qfn evaluation board lite 73s1210f - eb - lite 6 related documentation the following 73s1210f documents are available from teridian semiconductor corporation: 73s1210f data sheet 73s1210f evaluation board lite quick start guide tsc flash programmer model tfp2 user's manual 7 contact information for more information about teridian semiconductor products or to check the availabili ty of the 73s1210f contact us at: 6440 oak canyon road suite 100 irvine, ca 92618 - 5201 telephone: (714) 508 - 8800 fax: (714) 508 - 8878 email: scr.support@teridi an.com for a complete list of worldwide sales offices, go to http://www.teridian.com . downloaded from: http:///
ug_1210f_044 73s1210f evaluation board lite user gu ide rev. 1.1 25 revision history revision date description 1.0 february 6, 2008 first publication . 1.1 august 18 , 2009 changed the document title from 73s1210f development board user guide to 73s1210f evaluation board lite user guide . made minor bom modifications to remove obsolete parts. miscellaneous editorial modifications. downloaded from: http:///

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